GGNMOS ESD Protection Simulation

Application Example for Download

Gate grounded N-MOS (ggNMOS) transistor is a popular ESD protection device. The structure of a basic ggNMOS is illustrated at left. In a simple configuration, the gate, source and substrate terminals are grounded, while the drain terminal is connected to the I/O pad. When ESD stress occurs on the drain, and the drain voltage increases, the drain-substrate junction is reverse biased. Under sufficiently high voltage, avalanche breakdown occurs, and the generated holes drifts to the substrate contact, forming a large hole current. Since the substrate doping is typically not very high, this hole current leads to a voltage drop in the substrate that forward biases the source-substrate junction. The parasitic BJT transistor turns on when the emitter-base (source-substrate) voltage exceeds 0.6V, forming a new, stronger conduction path to shunt the drain current. More importantly, since higher current is flowing through the high E-field region near the drain, it takes lower E-field to maintain the same avalanche hole generation rate and emitter-base voltage. Therefore, the drain voltage reduces as current increases, leading to a snapback in the current-voltage characteristics.

Simulation Considerations

In our simulation, the ggNMOS device is triggered by impact ionization processes in the drain-substrate junction, so impact ionization models are important. In Genius, a few impact ionization models are implemented, as detailed in the user's guide.

Because of the high level of current, as well as the high voltage, in the ggNMOS device, lattice heating is significant. When temperature is too high in the device, permanent damage is resulted in. Therefore, it is critical to include lattice heating effects in the simulation of ggNMOS devices. Lattice temperature equations can be enabled in Genius simulation. Additionally, Genius allows the user to specify thermal boundary conditions to model heat lost at the surroundings.

Since ESD protection devices are connected directly to I/O pads, the large parasitics at IC pin lead and bond wire could affect the performance significantly. Genius can interface with circuit simulator NG-SPICE to perform circuit-device mixed-mode simulation, where these parasitic components, as well as other electrical components in the test set up, can be modeled.

Simulated Transient Characteristics

The simulated drain voltage of the ggNMOS under a 0.7A standard TLP waveform is shown in figure below(left). The drain voltage snaps back at about 14V. The snap-back behavior can be alternatively plotted in figure below(right).

To understand the device operation better, we examined the electron concentration in ggNMOS at 2ns, as shown in figure below. It is obvious that the parasitic BJT is turned on, and huge amount of electrons are injected to the substrate to form the conductive channel.

The lattice temperature at 2ns, 10ns, 15ns and 25ns are shown in figure below. The peak temperature can exceed the melting temperature of silicon and cause permanent damage to the device. A post-processor is written to extract the peak temperature in the device, and report to the user if it exceeds a prescribed threshold.